The life cycles of products tend to become shorter and shorter because needs for information processing in information processing terminals have been diversified so that standards for communication systems and signal processing have changed kaleidoscopically in recent years. Devices having functions capable of being changed by programs are useful to cope with the shortening of the life cycles of products. A DSP (Digital Signal Processor) and a microprocessor are examples of these devices. In the DSP or microprocessor, an instruction program can be changed to provide the degree of freedom of the program in the instruction level. The DSP or microprocessor is however inferior in processing performance to an ASIC (Application Specified IC) limited to a specific purpose of use.
Therefore, a programmable logic device having circuit configuration allowed to be changed flexibly by a program has attracted attention as a device having both processing performance of an ASIC and programmability of a microprocessor. Although there are several kinds of programmable logic devices, an FPGA (Field Programmable Gate Array) is representative of the programmable logic devices. Although these devices have a merit that the circuit configuration of each device can be changed by a program, these devices have a demerit in increase in area, increase in electric power consumption, etc., as compared with the ASIC.
On the other hand, as a method for reducing the area of a programmable logic device, for example, there is a method as follows (see Patent Document 1). In Patent Document 1, wiring resources for connecting logical elements on the programmable logic device are formed from two wiring resources, that is, a first resource having a communication speed called “normal speed” and a second resource having a communication speed higher than that of the first resource. As for the proportion of these two resources, the first resource accounts for a large part of the wiring resources and the second resource accounts for a small part thereof. Thus, when the second resource is used for only part of the wiring requiring high speed communication while the first resource is used for normal communication, all wirings need not be designed in accordance with a high speed so that increase in area caused by the high speed design can be suppressed.    Patent Document 1: International Patent Publication No. 2002-538634